Complementary data signals are commonly used in a variety of integrated circuits, such as memory devices, including a synchronous dynamic random access memory (SDRAM) 10 shown in FIG. 1. The SDRAM 10 includes an address register 12 that receives either a row address or a column address on an address bus 14. The address bus 14 is generally coupled to a memory controller (not shown in FIG. 1). Typically, a row address is initially received by the address register 12 and applied to a row address multiplexer 18. The row address multiplexer 18 couples the row address to a number of components associated with either of two memory banks 20, 22 depending upon the state of a bank address bit forming part of the row address. Associated with each of the memory banks 20, 22 is a respective row address latch 26 which stores the row address, and a row decoder 28 which applies various signals to its respective array 20 or 22 as a function of the stored row address. The row address multiplexer 18 also couples row addresses to the row address latches 26 for the purpose of refreshing the memory cells in the arrays 20, 22. The row addresses are generated for refresh purposes by a refresh counter 30 which is controlled by a refresh controller 32.
After the row address has been applied to the address register 12 and stored in one of the row address latches 26, a column address is applied to the address register 12. The address register 12 couples the column address to a column address latch 40. Depending on the operating mode of the SDRAM 10, the column address is either coupled through a burst counter 42 to a column address buffer 44, or to the burst counter 42 which applies a sequence of column addresses to the column address buffer 44 starting at the column address output by the address register 12. In either case, the column address buffer 44 applies a column address to a column decoder 48 which applies various signals to respective sense amplifiers and associated column circuitry 50, 52 for the respective arrays 20, 22.
Data to be read from one of the arrays 20, 22 is coupled to the column circuitry 50, 52 for one of the arrays 20, 22, respectively. The data is then coupled to a data output register 56 which applies the data to a data bus 58. Data to be written to one of the arrays 20, 22 is coupled from the data bus 58 through a data input register 60 to the column circuitry 50, 52 where it is transferred to one of the arrays 20, 22, respectively. A mask register 64 may be used to selectively alter the flow of data into and out of the column circuitry 50, 52, such as by selectively masking data to be read from the arrays 20, 22.
The above-described operation of the SDRAM 10 is controlled by a command decoder 68 responsive to high level command signals received on a control bus 70. These high level command signals, which are typically generated by a memory controller (not shown in FIG. 1), are a clock enable signal CKE*, a clock signal CLK, a chip select signal CS*, a write enable signal WE*, a row address strobe signal RAS*, and a column address strobe signal CAS*, which the "*" designating the signal as active low. The command decoder 68 generates a sequence of command signals responsive to the high level command signals to carry out the function (e.g., a read or a write) designated by each of the high level command signals. These command signals, and the manner in which they accomplish their respective functions, are conventional. Therefore, in the interest of brevity, a further explanation of these control signals will be omitted.
To best understand the disclosed embodiment of the inventive sense amplifier, it is best to have an understanding of a portion of the circuitry conventionally used in the column circuitry 50, 52 and the data output register 56 in the SDRAM 10 of FIG. 1. The column circuitry 50, 52 for each of the memory arrays 20, 22 typically includes a sense amplifier (not shown) for each column in each array 20, 22, respectively. This sense amplifier will be referred to as a digit line sense amplifier to distinguish it from sense amplifiers of the type described and claimed herein which will sometime be referred to as an array sense amplifier. The digit line sense amplifier in the column circuitry 50, 52 for an addressed column receives complimentary signals from a pair of complimentary digit lines. The digit lines are, in turn, coupled to a pair of complimentary I/O lines by column addressing circuitry which is not shown in FIG. 1 for purposes of brevity. There are generally a pair of I/O lines included in each of the column circuitry 50, 52, i.e., one for each of the arrays 20, 22. Each pair of I/O lines is selectively coupled by a pair of complimentary data lines to the complimentary inputs of an array sense amplifier (not shown) included in the column circuitry 50, 52 or the data output register 56. The output of the active array sense amplifier is coupled to a bit of the data bus 58.
In the past, attempts have been made to expedite testing by reading data from the arrays 20, 22 using data compression in which the data from two or more memory cells in the arrays 20, 22 are combined to provide a single output. One technique for accomplishing this data compression has been by coupling the output terminals of several array sense amplifiers to comparison circuitry fabricated on the integrated circuit along with the memory device 10. Although this approach does expedite testing, there are nevertheless several problems in implementing this concept in increasing compact integrated circuit memory devices. At least some of these problems could be largely solved if data compression could occur "upstream" from the array sense amplifier. However, upstream data compression would inherently require that the array sense amplifier be capable of amplifying a pair of signals that may not be complimentary of each other. Unfortunately conventional array sense amplifiers are incapable of amplifying non-complimentary input signals, particularly amplifiers that can sufficiently amplify input signals that, while complementary, differ only slightly from each other. Yet substantial amplification of the input signals is necessary so that the outputs of the array sense amplifier can be interpreted as logic "0" and "1" values.
One embodiment of a conventional sense amplifier circuit is illustrated in FIG. 2. The sense amplifier circuit 100 includes a pair of PMOS transistors 112, 114 having their sources connected to a supply voltage VCC and their gates coupled to each other and to the drain of one of the PMOS transistors 114. In this configuration, the transistors 112, 114 act as current mirrors so that the current I.sub.1 through the PMOS transistor 112 will be the same as the current I.sub.2 through the PMOS transistor 114.
The drains of the PMOS transistors 112, 114 are connected to the drains of respective NMOS sense transistors 120, 122. The gate of one sense transistor 120 is coupled to the data line D while the gate of the other sense transistor 122 is coupled to the complement of the data line D*. The sources of the sense transistors 120, 122 are coupled to ground through an NMOS bias transistor 126 which is biased on by coupling its gate to a voltage V.sup.1 which may be VCC or some other voltage between VCC and V.sub.T, the transition voltage of the transistor 126.
Although not required for the operation of the sense amplifier circuit 100, a PMOS equilibration transistor 130 is coupled between the drains of the sense transistors 120, 122 to equalize their voltages prior to receipt of the complementary data signals D and D*. The drain of one of the sense transistors 120 is used as the output line 132 of the sense amplifier circuit 100.
The operation of the sense amplifier circuit 100 illustrated in FIG. 2 will be explained using exemplary voltage levels which are indicated in parentheses in FIG. 2. However, it will be understood that these voltage levels are provided only as examples since other voltage levels are often present in conventional sense amplifiers. Further, it will be assumed that VCC for the sense amplifier circuit 100 is 3.3 volts and that a logic "1" level of 3.2 volts is coupled to the gate of the sense transistor 120 while a logic "0" voltage of 2.9 volts is coupled to the gate of the sense transistor 122.
Insofar as the voltage applied to the gate of the sense transistor 120 is greater than the voltage applied to the gate of the sense transistor 122, the transistor 120 is turned on to a greater degree than transistor 122. As a result, the source to gate resistance of the transistor 120 is lower than the source to gate resistance of the transistor 122. As mentioned above, the PMOS transistors 112, 114 are configured as a current mirror so that I.sub.1 and I.sub.2 are equal to each other. As a result, the voltage across the lower resistance sense transistor 120 is lower than the voltage across the higher resistance sense transistor 122. For this reason, using the example shown in FIG. 2, the drain of the sense transistor 120 is at 2.7 volts while the drain of the sense transistor 122 is at 3.3 volts. The sense amplifier circuit 100 has thus boosted the differential between the complementary signals from 0.3 volts (i.e., 3.2-2.9) to 0.6 volts (i.e., 3.3-2.7). Prior to applying the complementary signals to the gates of the sense transistors 120, 122, the equilibration transistor 130 is turned on by conventional circuitry to place the drains of the sense transistors 120, 122 at a suitable voltage between 2.7 volts and 3.3 volts, e.g. 3.0 volts. As a result, it is necessary for the drain of either transistor 120, 122 to change by only 0.3 volts when the differential data signals are applied to the gates of the sense transistors 120, 122. The bias transistor 126 is provided to raise the absolute voltages at the drains of the source transistors 120, 122 to a suitable level since the voltage across the sense transistors 120, 122 is boosted by the voltage across the bias transistor 126. The sense amplifier circuit 100 is thus a differential amplifier that compares the voltage applied to the gate of one sense transistor 120 to the voltage applied to the gate of the other sense transistor 122.
In operation, the voltage at the drain of the sense transistor 120 changes to a greater extent than the voltage at the drain of the sense transistor. 122 because the drain of the PMOS transistor 112 is not coupled to the gate of the transistor 112. On the other hand, coupling the drain of the PMOS transistor 114 to its gate limits the magnitude of the change in voltage at the gate of the sense transistor 122. Thus, in practice, the drain of the sense transistor 120 is generally preferred for use as the output node thus causing the sense amplifier circuit 100 to function as an inverting differential amplifier.
In practice, the sense amplifier circuit 100 illustrated in FIG. 2 is commonly used in the quad configuration shown in FIG. 3. The sense amplifier 140 shown in FIG. 3 uses two amplifier stages 142, 144 each of which consists of two sense amplifiers 100 of the type illustrated in FIG. 2.
As mentioned above, the drain of the PMOS transistor 112 changes to a larger extent than the voltage on the drain of the PMOS transistor 114 because the drain of the transistor 112 is not coupled to the gates of the PMOS transistors 112, 114. For this reason, using the drains of the sense transistors 120, 122 as differential outputs of each sense amplifier circuit 100 would result in an unbalance. Two sense amplifiers 100 are therefore used for each stage 142, 144. Further, two stages 142, 144 are used to provide a sufficient voltage differential on output lines 150, 152.
Each of the sense amplifiers 100 operates in essentially the same manner as explained above with reference to FIG. 2. Thus, the sense amplifier circuit 100a receives the data input D and its complement D* and generates an output corresponding to D*-D. Although an output signal is also generated at the drain of the PMOS transistor 114, it is not used because, as explained above, the change in voltage as a function of D*-D is greater at the drain of the PMOS transistor 112. Similarly, the sense amplifier circuit 100b receives the data signal D and its complement D* and generates an output signal that is proportional to D-D*. Since the output of the sense amplifier circuit 100b is also generated at the drain of the PMOS transistor 112, the sense amplifier circuit 100b has essentially the same topography as the sense amplifier circuit 100a. As a result, the change in voltage at the output of the sense amplifier circuit 100a corresponding to D*-D changes by the same magnitude as the output of the sense amplifier circuit 100b responsive to D-D*.
The balanced outputs from the first stage 142 are then applied to the second stage 144. More specifically, the sense amplifier circuit 100c receives the output of the sense amplifier circuit 100a (which is proportional to D-D*) and compares it to the output of the sense amplifier circuit 100b (which is proportional to D*-D). The output signal on output line 150 is thus proportional to (D-D*)-(D*-D) or 2D-2D*. Similarly, since the output signal of the sense amplifier circuit 100d is proportional to the output of the sense amplifier circuit 100a less the output from the sense amplifier circuit 100b, the output of the sense amplifier stage 144 on output line 152 is proportional to (D*-D)-(D-D*) or 2D*-2D. The differential output between lines 150 and 152 is thus (2D-2D*)-(2D*-2D) or 4D-4D*.
It will be apparent from the above formula and the explanation of the sense amplifier 140 shown in FIG. 3 that it is capable of amplifying only signals that are differential or complementary with respect to each other. However, there are some instances in which it is desirable for an array sense amplifier to be able to receive and amplify data signals that are not complementary with respect to each other. While a separate amplifier for amplifying non-complementary data signals could be provided for this purpose, providing this additional circuitry would increase the cost of memory devices containing both types of amplifiers. Providing separate complementary and non-complementary sense amplifiers may not be cost effective in many situations since the data signals may be non-complementary for very limited operating modes, such as in production test modes. There is therefore a need for a sense amplifier that can amplify complementary data signals in normal operation yet, without adding an extensive amount of circuitry, can also amplify data signals that are not complementary with respect to each other.